1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, but not by way of limitation, to a method and system for testing a semiconductor memory device at high speed using a data storage signal generated from an internal clock signal of the semiconductor memory device so as to increase the number of memory modules that can be simultaneously tested and reduce a test time for a unit memory module.
This application claims the benefit of Korean Patent Application No. 10-2006-0072248, filed on Jul. 31, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
As semiconductor memory devices become highly integrated, the time required to test the semiconductor memory devices is increased. Accordingly, high-speed test techniques have been developed in order to reduce the test time. Furthermore, methods for simultaneously testing a larger number of semiconductor memory modules have also been developed.
However, the number of semiconductor memory modules that can be simultaneously tested is restricted by the number of test channels of a test device, and the number of test channels is restricted by the number of signals applied to the semiconductor memory modules. The number of test channels indicates the number of memory modules that can be simultaneously tested by the test device. That is, the number of semiconductor memory modules that can be simultaneously tested is determined by the number of signals applied to the semiconductor memory modules.
The test device applies test data through test channels to semiconductor memory modules respectively corresponding to the test channels. In this case, a data strobe signal used to sample the test data is also applied to the semiconductor memory modules through a test channel. Thus, when the test device applies the data strobe signal to the semiconductor memory modules, the number of test channels is reduced. This restricts the number of semiconductor memory modules that can be simultaneously tested.